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Altera_Forum
Honored Contributor
11 years agoEnable L2 Cache
Hi! Is there an simple(!) example on using the L2 Cache (using hwlib)? My current test project places some code(some few KB) at 32MB offset (0x0200 0000), so i guess it ends up in DDR R...
Altera_Forum
Honored Contributor
11 years agoI think I may know the problem that you have. Something similar happened to me too :)
The issue seems to be that you just define the 64MB that you want. This makes the rest of the memory inaccessible. Then the Debugger tries to access other memory (or your application tries to access some peripheral that is not defined in the MMU table) and everything blows up. What you need to do is provide MMU tables for all the memory, describing which areas are cacheable and which not (like peripherals). Please take a look at the additional HWLIBs examples at http://www.altera.com/support/examples/soc/soc.html. Specifically get the example called "Quad SPI". Inside you will see a working example on using caches:- Files "alt_pt.c" and "alt_pt.h" contain the MMU tables.
- File "qspi_demo.c" contains the function "system_init()" which, among other things, sets up the MMU and caches.
- Go to www.altera.com
- Click on "Support"
- Click on "Design Examples"
- Click on "SoC"