Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
22 years ago

Dynamic Bus Sizing on Avalon Bus

Hi all,

To access a 8-Bit Port on a DSP (TMS320 / HPI8) I've implemented an 'Interface to User Logic' as Avalon memory slave. This module has 8-Data-Bits, 11 Addr-Bits, WRn, RDn, and CSn, all shared on Avalon except CSn.

Because of its internal 16-Bit structure and 8-Bit interface a double access is necessary to read/write data via this interface while A[0] specifies upper or lower byte. So 'Dynamic Bus Sizing' should be the perfect solution.

With a 16-bit-write to the port all seems to be ok: two WRn strobes with A0 changing from 0 to 1. But in a 16-Bit-read command four read cycles (RDn) are generated, reading a whole 32-Bit word on succeeding addresses. Disassembling the appropriate code shows 'ldhu r2,0(r2)' is used (once) in this context.

Because the DSP-Interface has auto increment when reading its port, additional strobes increment internal address counter.

My question is: How can I ensure that a 16-bit read on a 8-bit location produces only two read cycles on Avalon bus?

Has anybody an answer?

Mike

-----------------------------------

Quartus: 4.1 Build 208 SP2

NIOS II SOPC Builder: 4.1 Build 208

Windows XP Pro

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    22 years ago

    Mike,

    It's true that reads and writes are handled differently wrt dynamic bus sizing. Your writes are working as expected because the Nios2 asserts 2 of the 4 byteenable signals on the data master, and the dynamic bus sizing state machine takes this into account. On reads, the dynamic bus sizing logic ignores byteenable, and assumes full-width reads, as you've observed.

    Here are two solutions:

    1) Define the port as an 8-bit native slave (Avalon Register Slave in the interface to user logic). Two accesses will be required for each 16-bit read or write, but at least it should work.

    2) Create a bridge component with a 16-bit native aligned slave and a 16-bit master. The bridge simply passes access across to the actual 8-bit slave. Because its master is 16-bit data width, the dynamic bus circuitry will work as you need. This approach is a bit more work but would yield higher performance. If you want to go this way, I recommend using the new "Create New Component" feature in SOPC Builder in QII4.2 (it supports components with multiple slaves/masters, unlike the interface to user logic which is restricted to a single master or slave).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    22 years ago

    Thanks for your response

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    1) Define the port as an 8-bit native slave (Avalon Register Slave in the interface to user logic). Two accesses will be required for each 16-bit read or write, but at least it should work.[/b]

    --- Quote End ---

    I&#39;ve tried this but a register slave doesn&#39;t use dynamic bus sizing and makes one single access everytime. So to access a 16-bit word through a 8-bit port needs software overhead.

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    2) Create a bridge component with a 16-bit native aligned slave and a 16-bit master. [/b]

    --- Quote End ---

    I realized now that I have to add a special interface anyhow because the DSPs are using big endian coding internally.

    Mike