Dynamic Bus Sizing on Avalon Bus

Mike,

It's true that reads and writes are handled differently wrt dynamic bus sizing. Your writes are working as expected because the Nios2 asserts 2 of the 4 byteenable signals on the data master, and the dynamic bus sizing state machine takes this into account. On reads, the dynamic bus sizing logic ignores byteenable, and assumes full-width reads, as you've observed.

Here are two solutions:

1) Define the port as an 8-bit native slave (Avalon Register Slave in the interface to user logic). Two accesses will be required for each 16-bit read or write, but at least it should work.

2) Create a bridge component with a 16-bit native aligned slave and a 16-bit master. The bridge simply passes access across to the actual 8-bit slave. Because its master is 16-bit data width, the dynamic bus circuitry will work as you need. This approach is a bit more work but would yield higher performance. If you want to go this way, I recommend using the new "Create New Component" feature in SOPC Builder in QII4.2 (it supports components with multiple slaves/masters, unlike the interface to user logic which is restricted to a single master or slave).