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Altera_Forum's avatar
Altera_Forum
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21 years ago

Dude, where are my JTAG pins

Hi, To my surprise, after creating a Nios-II system using SOPC builder and specifying 'level1' for the 'JTAG debug module', I see no JTAG pins on the symbol when I return to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is there out anybody out that tests the nios II at a system (complete device) level with an RTL simulation? (or 'real' SDF timing).

Surely this is part of a 'standard' SOPC design flow.

How else would verification with 'real' SDF timing be achievable without having a method of doing this?? It would be impossible any other way in my eyes and surely this is something that needs to be covered for anything that is timing critical.

Please enlighten me. Somebody....