Dude, where are my JTAG pins

I suspect there may be a tcl interface to control the rtl of the buried sopc from the top level as there doesn't appear to be any vhdl models for the Jtag interface (and as previously stated you can't actually see the Jtag pins in a rtl simulation anyway).

From my perspective any combination of tcl script / vhdl testbench / both to exercise the individual registers within the sopc from the complete device top level for the purposes of simple writes / reads would be fine :).

Please help :).

Winston.