Dude, where are my JTAG pins

I am trying to access the Jtag pins in my RTL simulation also. Not having much luck :(.

I want to test the system level design at the top level with no software interaction in a 'real' system (as part of an automated self-checking VHDL testbench). (And as a software independant check.)

[I've had a look at the PLI and this does not support the SOPC Jtag UART which is what the design I am looking at is using.]

I am thinking that over the Jtag pins is the best option.

Using the System Console to exercise the programmed chip is fine, but to exercise the RTL design what am I supposed to do without access to the Jtag pins?

I feel a little lost :(....

[Also; can somebody provide me with a URL to where the Altera communications over the Jtag port to the NiosII is decribed (serial message and format sent in through TDI for read/write/etc).]