Dude, where are my JTAG pins

Roland,

The JTAG connections to the outside world are hard-wired on the device. However, Altera has (proprietary) logic that allows us to connect to JTAG with things like processors. Nios II, or more appropriately, the debug core if selected, talks to this logic for JTAG connectivity. The same technology is used with the signal tap logic analyzer, which adds no pins to your design, but allows you to do logic analyzer-type activities through your JTAG download cable.

For purposes of simulating the Nios II CPU, with or without the debug core, yes, JTAG is transparent. However, we do include simulation support for our other JTAG peripheral in the kit (the JTAG UART). Note that the simulation support for this does not give you a wiggling TDI/TDO/TCK, but rather, a host-style interface where you can send & receive characters, and Nios gets those from the peripherals; the JTAG logic is hidden.