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Altera_Forum's avatar
Altera_Forum
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21 years ago

Dude, where are my JTAG pins

Hi, To my surprise, after creating a Nios-II system using SOPC builder and specifying 'level1' for the 'JTAG debug module', I see no JTAG pins on the symbol when I return to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

So this means that JTAG is hardwired from the Nios-II core and the FPGA JTAG chain ? That is kind of weird because the Nios-II can be mapped anywhere on the FPGA surface, right ? So that would mean that everywhere on the FPGA there are hard wired connections that lead towards the JTAG pins on the FPGA.

Also, (just want to make this sure) : JTAG logic in the Nios-II is not simulated when I run a simulation ?

Bye,

Roland.