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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dual port ram memory does not react to read signals in time

Dear All,

i have designed a system which contains a dual port ram( Avalon MM slave )

one port is used to "talk" with the Nios and the other one is talking to a Multiplexed Addres bus(PPI) which i made as an Avalon MM Master.

As soon as I perform a read from the PPI. I assert the avm_master_address, avm_master_read like described in the specification.

then the data should appear on the avm_master_readdata the next clock cycle if avm_master_waitrequest is not asserted. In my case the avm_master_waitrequest is asserted for one clockcycle, so the data would be present the next clockcycle, which is fine by me.

but the data is not present that clockcycle. it changes to the correct data after maybe 20 to 35 clockcycle and then avm_master_request is not high.

What could be problem here??

picture of signaltap can be found here:

h ttp://img402.imageshack.us/img402/8173/strangewaitrequest.png

(need to remove the spaces )

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It's hard to tell in the signal tap capture but the master should be asserting read for two clock cycles. The first cycle the waitrequest happens to fire meaning the read has not completed until the 2nd cycle.

    Note: if you use a pipelined read master (use the 'readdatavalid' signal) the fabric will not need to generate waitrequest on the first cycle of each on-chip memory read. This will effectively double your memory bandwidth assuming the master can keep up.