Dual port ram memory does not react to read signals in time

It's hard to tell in the signal tap capture but the master should be asserting read for two clock cycles. The first cycle the waitrequest happens to fire meaning the read has not completed until the 2nd cycle.

Note: if you use a pipelined read master (use the 'readdatavalid' signal) the fabric will not need to generate waitrequest on the first cycle of each on-chip memory read. This will effectively double your memory bandwidth assuming the master can keep up.