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Altera_Forum
Honored Contributor
14 years agoDual port memory corruption
We have system that is using an M9K memory block for IPC between two nios2 cpus. CPU A accesses it as tightly coupled data memory, CPU B via the data port and Avalon bus (no data cache on eithe...
Altera_Forum
Honored Contributor
13 years agoI just looked at this doc and the section "Mixed-Port RDW" suggests that you can't use a dual clocking scheme with mixed ports and the old data option all at the same time: http://www.altera.com/literature/ug/ug_ram_rom.pdf
If that's really true then that's a bug with the on-chip memory component. If this is true I'm not sure why Quartus allowed the compile to go through unless the memory component does something to the instantation that makes it work.