Forum Discussion
Altera_Forum
Honored Contributor
14 years agoDual port memory corruption
We have system that is using an M9K memory block for IPC between two nios2 cpus. CPU A accesses it as tightly coupled data memory, CPU B via the data port and Avalon bus (no data cache on eithe...
Altera_Forum
Honored Contributor
14 years agoWhat might be happening is without constraints the fitter is putting most of it's effort into paths that are failing due to a lack of constraints and causing other valid paths to fail in the process. The fitter optimizes based on slack times so if you had some paths that should be false paths and they have the worst slack times due to a lack of constraints the fitter will work extra hard on those paths. So it could be the fitter was working hard on improving the slack time to LEDs instead of focusing on on-chip paths like between Nios II and the dual-port RAM.