Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Dual access block ram access from nios and custom vhdl

First, Id like to say I'm new to using Altera FPGA's so sorry if this is very simple. I have implemented a dual access block ram in SOPC. One side goes to the nios-II core so i can read and write fro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

SOPC Builder provides arbitration logic for you but you will need to handle the hazards of accessing the same address. For example if the read and write masters access address 0-1023 you will not know which master will gain arbitration to any of the locations first. If you can prevent the masters from accessing the same range at the same time then you can avoid the data hazard.