DTB (Device Tree Blob Files) Step by Step Guide DE1-SoC ** HELP ! ** GPIO Q14.0

Question

I am developing a design on the DE1-SoC. I wanted to be able to drive some more GPIO from the HPS. The pins that were already GPIO in the GHRD work fine. After clicking the button in the HPS tab in QSYS, resolving the conflicts, I expected the new GPIO to be under HPS control. But no matter what I cannot drive them from the HPS.

I suspect (is this right?) that the GPIOs aren't working because I need a new device tree blob file. This is where things start getting difficult. The socfpga.dtb that is on the SD card image works. But it does not match the what is present in the GHRD, indeed when I swap the file on the card with the file in the GHRD, the ethernet port stopped working and there were some complaints on boot up about missing I²C.

What is really, really frustrating is that it appears there is no way I can build the *.dtb file from any of the files supplied with the GHRD.

There seems to be much conflicting information on this subject. For example it seems a clock.xml (Q13.1) file was needed but now isn't.

How do I create a suitable board.xml file?

Failing this it would helpful if I could replicate the process that built the socfpga.dtb that is already present on the SD card.

I hope some-one can help!

altera_forum · Answer

I am not familiar with that particular board but I can tell you how it works for the Altera Cyclone V Development Kit.

There are separate GSRD (Golden System Reference Designs) releases for each tool versions (13.1, 14.0 and 14.0.1). Each has its own version of GHRD (Golden Hardware Reference Design), including the required XML files. There are also instructions on how to generate the DTB for each version.

See http://rocketboards.org/foswiki/documentation/gsrd

Note that the information required by Linux varies between kernel versions. Also, the Device Tree generator evolved between tool versions (13.1 to 14.0.1).

If the above does not help, I would suggest trying to contact that particular board supplier.

altera_forum · Answer

Thanks for the reply. The above doesn't really help, because although the SOPC info file is readily available I don't know what is contained or should be contained in the two xml files:-

board ghrd_5astfd5k3_board_info.xml

board hps_common_board_info.xml

I can't find any literature on these xmls files to date! Any suggestions on this people?

I can't even re-create the dtb file that is found on the DE1-SoC Linux image!

altera_forum · Answer

I looked around and have only managed to locate the following resources:

Terasic Page for DE-1 SoC Board: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=836&partno=4
Rocketboards resource page for DE-1 SoC Board: http://rocketboards.org/foswiki/documentation/terasicde1socdevelopmentandeducationboard#a_42resources_42

Unfortunately they do not seem to provide all the files you need to re-compile everything (including generating DeviceTree) from scratch.

The Terasic page says that "please note that all the source codes are provided 'as is'. for further support or modification, please contact terasic support <support@terasic.com> and your request will be transferred to terasic design service." You may want to try contacting them at that email address and request all the files.

Regarding the 'clock.xml', it is not required anymore because the latest version of the DeviceTree Generator knows how to extract the clock settings from the latest format of the .sopcinfo file, and output it directly in the .dtb file. By 'latest' I mean v 14.0 and higher. The newly added '--clocks' option instructs the DeviceTree Generator to do that.

Also, I see you mention the file 'ghrd_5astfd5k3_board_info.xml'. That is the name for the Arria V designs, and not for the Cyclone V designs. Just wanted to mention it, in case it helps.

I recommend the following:

Request from support@terasic.com all the files required to rebuild the image for their board from scratch
Rebuild their system and see it working
Modify the system according to your needs, including the DeviceTree Generator XML files

Sorry I could not help more.

altera_forum · Answer

Well I was wrong to think I needed a new device tree blob. Actually I needed to recompile the preloader, which was much more straightforward.

To cut a long story short, my HPS GPIO is now working as I set it up in QSYS! :)

altera_forum · Answer

--- Quote Start ---

I am not familiar with that particular board but I can tell you how it works for the Altera Cyclone V Development Kit.

There are separate GSRD (Golden System Reference Designs) releases for each tool versions (13.1, 14.0 and 14.0.1). Each has its own version of GHRD (Golden Hardware Reference Design), including the required XML files. There are also instructions on how to generate the DTB for each version.

See http://rocketboards.org/foswiki/documentation/gsrd

Note that the information required by Linux varies between kernel versions. Also, the Device Tree generator evolved between tool versions (13.1 to 14.0.1).

If the above does not help, I would suggest trying to contact that particular board supplier.

--- Quote End ---

I have questions about soc software lab instrutions in module 4.2.4

http://www.alteraforum.com/forum/attachment.php?attachmentid=11240&stc=1

I don't know how to halt the 'scroll_server' .

And just type ./init_leds.sh,it will reminds me :no such file or no directory

Can you help me how solve this problem?

Thank you !

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DTB (Device Tree Blob Files) Step by Step Guide DE1-SoC HELP ! GPIO Q14.0

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