I looked around and have only managed to locate the following resources:
Unfortunately they do not seem to provide all the files you need to re-compile everything (including generating DeviceTree) from scratch.
The Terasic page says that "
please note that all the source codes are provided 'as is'. for further support or modification, please contact terasic support <support@terasic.com> and your request will be transferred to terasic design service." You may want to try contacting them at that email address and request all the files.
Regarding the 'clock.xml', it is not required anymore because the latest version of the DeviceTree Generator knows how to extract the clock settings from the latest format of the .sopcinfo file, and output it directly in the .dtb file. By 'latest' I mean v 14.0 and higher. The newly added '--clocks' option instructs the DeviceTree Generator to do that.
Also, I see you mention the file 'ghrd_5astfd5k3_board_info.xml'. That is the name for the Arria V designs, and not for the Cyclone V designs. Just wanted to mention it, in case it helps.
I recommend the following:
- Request from support@terasic.com all the files required to rebuild the image for their board from scratch
- Rebuild their system and see it working
- Modify the system according to your needs, including the DeviceTree Generator XML files
Sorry I could not help more.
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