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Altera_Forum
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12 years ago

Download Bitstream to Cyclone V by using the FPGA manager

Hi, I like to upload the soc_system.sof via the FPGA manager. I use the source code of the U-Boot. I have ported it to VxWorks. I use the Altera Evaluation Board REV B. . Before I begin to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I can read the MSEL pins back as 0x8 and am programming the cd ratio to 0:0 and the cfgwdth to 1. Any ideas as to what else could cause this?