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Altera_Forum
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12 years ago

Download Bitstream to Cyclone V by using the FPGA manager

Hi, I like to upload the soc_system.sof via the FPGA manager. I use the source code of the U-Boot. I have ported it to VxWorks. I use the Altera Evaluation Board REV B. . Before I begin to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I'm having similar troubles. I was able to get past the 0xB01 by setting the msel for 32-bit mode. Which is msel[4:0] = 01000. However now I get 0xB09 CRC error and other strange behavior. CONF_DONE is flashing out of control during programming and eventually settles at being off. After running my program the jtag chain is lost until a hard reset.