does EPCS controller support DMA

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originally posted by bigboss25@Jun 29 2006, 07:34 PM

i would like to know if the epcs controller is able to handle dma transfer.

i would like to transfer nios2 code from epcs to sdram using dma at boot time, in order to boot as fast as possible.

i think that currently, if i'm not wrong, there is a firmware code (so the cpu) which handle this job. any idea ?

thanx all http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif

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The max clock rate of epcs is 40MHz.

So the data rate is less than 5MB/s.

With a proper boot code, the data rate can be handle well with PIO.

There will be little gain in using DMA.

This may be irrelevant, because of hippo&#39;s throughput analysis, but if offloading the data transfer to a DMA-like component is still of interest, read on:

The Avalon DMA cannot transfer data from the epcs component, because Avalon flow control doesn&#39;t work properly on that connection. The root of the problem is the way the epcs component produces read data:

1) an avalon master writes a dummy byte to the epcs component

2) the epcs component clocks out the dummy byte, and simultaneously receives data from the epcs flash chip

3) the received byte is available to be read in the epcs component rx register.

In a simple DMA <-> epcs component connection, there is no master to write dummy bytes into the epcs component, thus no received data. It _might_ work if, say, the Nios was writing the dummy bytes into the tx register, but ... why bother using a DMA if you have to tie up the processor anyway?

I suggest writing a custom component in the HDL of your choice (for importation with component editor), which writes and reads the epcs, and delivers the received data at a flow-control-equipped slave port, for the DMA to consume. Or, your custom component could have a master port, which would write its data directly to memory.