Does C2H generate to HDL verilog file?

The C2H compiler will generate a few of files:

1) The verilog/VHDL file that implements the function in hardware (top level of the Quartus II project)

2) A .tcl file that describes the hardware accelerator as a component ("" "")

3) A .tcl file that automatically hooks up the accelerator to the system (" ")

4) A .c wrapper file that includes the accesses to the hardware accelerator, this file gets linked in when you have the hardware accelerator selected in the Nios II IDE for the function implementation. (generated into the software application /Debug or /Release directory)

Thanks.

Maybe I blind or something. Because I couldn't find General HDL option in C2H GUI compiler. I also try ImpulseC and it does has option for me to generate to HDL (.v) file in folder HW.

Could you show me how to generate this or maybe I use a wrong software C2H. I'm using Nios II 9.0 IDE.

Sean

Page 31 shows what the setup should look like: http://www.altera.com/literature/ug/ug_nios2_c2h_compiler.pdf

I recommend reading that doc since it covers the flow and a bunch of other C2H topics.

Thanks,

I'm using Nios II 9.0 IDE free version that came with Quartus II, I wonder I can't generate verilog file because I don't have a full license.

Sean