Does a NIOS II need reset?

> how can I make it in a counter (flip-flops) without any problems then?

There's really no substitute for a good external reset ;-)

However, I do use the pll locked signal as an enable/clear input to a reset

counter that controls reset to a specific logic block. The counter's clock input

is an external clock signal, _not_ the output of the pll. And the counter

width is set based on the phase lock period from simulation (in my case

about 16x the counter's input clock). So, the counter is simply trying to

guarantee the stability of the pll locked signal before negating reset.

I haven't had any problems ... yet. But to be honest, I'm not particularly

comfortable with it either -- my knowledge just doesn't run deep enough

at this point 8-(

Given the number of posts to this topic -- an application note from the

experts would be a welcomed reference.