Does a NIOS II need reset?

Sorry about the delay (just got back from a vacation)

If you want to see in closer detail how a PLL output behaves, make a design with a PLL, and some circuit driven by it and do a simulation looking at the input clock, output clock, and reset signal and you will see why the delay is needed (although I sometimes get lazy and don't bother). When you look at the output from the PLL you'll see the first few output clocks out of phase and this could cause problems internal to the NIOS as it (PLL) locks the phase down.

Also thank you for the info about the locking signal not being completely valid to implement the reset (I like some of the others figured it could be used as well).