Do I need to set compile flag for Hardware Floating Point Custom Instruction Divider?

Hi,

I have the same problem with same software version. Maybe it's a bug, maybe one of the nios gurus can give us advise. Otherwise we have to enable it manually...

Thank you for reply in advance.

etricky

The custom instruction numbers are allocated by the sopc builder when the instructions are added. It isn't possible to assign specific numbers to specific instructions (they can be reordered, but the numbers have to be contiguous and start from zero). This is all a complete PITA since it means that the instruction definitions can't easily be built into the compiler, nor put into a header file.

Worse still, if you have a sopc image with more than one nios, and you want different subsets of custom instructions on each cpu you are in deep trouble.

Thank you for reply!

But the problem is, at the moment I can not use the CI floating point division. I have enabled the division in the floating point custom instuction in SOPC Builder. Every time I run BSP Editor I get

# Hardware Floating Point Custom Instruction without Divider present.

ALT_CFLAGS += -mcustom-fpu-cfg=60-1

ALT_LDFLAGS += -mcustom-fpu-cfg=60-1

and I think it should be -mcustom-fpu-cfg=60-2, right?

But manually changing seems not to work for me with ci floating point division. Do you have some comments?

I have used the standard CI Tutorial from Altera, here are the results

--Performance Counter Report--

Total Time: 0.00193648 seconds (242060 clock-cycles)

+---------------+-----+-----------+---------------+-----------+

| Section | % | Time (sec)| Time (clocks)|Occurrences|

+---------------+-----+-----------+---------------+-----------+

|FP CI ADD | 4.55| 0.00009| 11017| 1000|

+---------------+-----+-----------+---------------+-----------+

|FP SW ADD | 42.4| 0.00082| 102575| 1000|

+---------------+-----+-----------+---------------+-----------+

--Performance Counter Report--

Total Time: 0.00193874 seconds (242343 clock-cycles)

+---------------+-----+-----------+---------------+-----------+

| Section | % | Time (sec)| Time (clocks)|Occurrences|

+---------------+-----+-----------+---------------+-----------+

|FP CI SUBTRACT | 4.55| 0.00009| 11016| 1000|

+---------------+-----+-----------+---------------+-----------+

|FP SW SUBTRACT | 42.8| 0.00083| 103763| 1000|

+---------------+-----+-----------+---------------+-----------+

--Performance Counter Report--

Total Time: 0.00212669 seconds (265836 clock-cycles)

+---------------+-----+-----------+---------------+-----------+

| Section | % | Time (sec)| Time (clocks)|Occurrences|

+---------------+-----+-----------+---------------+-----------+

|FP CI MULTIPLY | 4.52| 0.00010| 12017| 1000|

+---------------+-----+-----------+---------------+-----------+

|FP SW MULTIPLY | 50| 0.00106| 132823| 1000|

+---------------+-----+-----------+---------------+-----------+

--Performance Counter Report--

Total Time: 0.00498763 seconds (623454 clock-cycles)

+---------------+-----+-----------+---------------+-----------+

| Section | % | Time (sec)| Time (clocks)|Occurrences|

+---------------+-----+-----------+---------------+-----------+

|FP CI DIVIDE | 40.1| 0.00200| 250195| 1000|

+---------------+-----+-----------+---------------+-----------+

|FP SW DIVIDE | 38.9| 0.00194| 242463| 1000|

+---------------+-----+-----------+---------------+-----------+

Thank you,

etricky

I've just look at the gcc sources and done some quick tests (gcc3).

Setting -mcustom-cpu-cfg=60-2 or 73-2 does cause a custom instruction to be generated for divide, 60-1 doesn't.

Adding -mcustom-fdivs=nnn is also enough.

Thank you!

Now every thing is fine!

Hmmm.... I wonder what is in the Altera defined FP custom instruction TCL that lets them assign instruction numbers that don't start from zero.

The standard stuff for adding custom instructions gives you no choice at all.

The actual decode logic generated ignores bits that aren't needed to select between the configured instructions.