Forum Discussion
Altera_Forum
Honored Contributor
21 years agoDMA
Hello I have problem with the DMA controller So, i have 2 memory and with the DMA i would like to transferer data from the first memory in the second. When i declare the DMA i have to p...
Altera_Forum
Honored Contributor
21 years agoI tested with an Altera FIFO (with show-ahead option activated) and it's ok. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif
The thing is that now I need another RAM but it can't be a FIFO: a control unit gives it the address for writing and RAM gets out the data sequentially if "NiosRead" is high. The problem is reading data from my module again: the first time is just fine, but the second time I run the program the first datum is repeated and the value# 8 is lost. Here is the VHDL code: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY ram_idct_out IS PORT( NiosCS : IN std_logic; NiosRead : IN std_logic; NiosReset : IN std_logic; clk : IN std_logic; data_in : IN std_logic_vector (8 DOWNTO 0); dir_w : IN std_logic_vector (5 DOWNTO 0); write : IN std_logic; data_out : OUT std_logic_vector (8 DOWNTO 0) ); -- Declarations END ram_idct_out ; ARCHITECTURE flow OF ram_idct_out IS -- Architecture declarations TYPE memory_type is array (63 DOWNTO 0) of std_logic_vector(8 DOWNTO 0); SIGNAL memory : memory_type; SIGNAL rd_addr : integer range 63 DOWNTO 0; SIGNAL wr_addr: integer range 63 DOWNTO 0; BEGIN ----------------------------------------------------------------- process0 : PROCESS (clk, NiosReset) ----------------------------------------------------------------- BEGIN -- Asynchronous Reset IF (NiosReset = '1') THEN -- Reset Actions rd_addr <= 0; data_out <= (OTHERS => '0'); ELSIF (clk'EVENT AND clk = '1') THEN data_out <= memory(rd_addr); IF NiosRead = '1' AND NiosCS = '1' THEN IF rd_addr = 63 THEN rd_addr <= 0; ELSE rd_addr <= rd_addr + 1; END IF; END IF; IF write = '1' THEN memory(wr_addr) <= data_in; END IF; END IF; END PROCESS process0; -- Architecture concurrent statements wr_addr <= conv_integer(unsigned(dir_w)); END flow; Could you please help me? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif Thanks!!!! By the way, I have to add another DMA for reading, I thought that it could work out with only one (for writing and reading).