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Altera_Forum's avatar
Altera_Forum
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20 years ago

DMA transfer problem

Hi, I use Nios3.1, QuartusII 4.0 and APEX20K. And I use Modelsim to simulate my system.

When I use DMA to transfer 20 data, I find a strange problem.

The DMA transfer one data per clock between fisrt 10 data. After sending the first 10 data, the DMA will stop one clock time. Then it will transfer the next "two" data, and still stop one clock time after sending the "two" data. This situation continue for the remaining data transfer.

Does anyone can tell me why this happen?? Or how to solve this problem?

Thanks a lot http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    pipiwau,

    I think the answer lies in the DMA master signals. The DMA must be able to continuously read data in order to continuously write data to your memory. If you look at the DMA read_waitrequest, it is going high after several reads... once this happens the DMA must stall to wait for more read data, and therefore must also stall before writing that data to your memory.

    Perhaps the memory you are reading from is shared with another master that is accessing it simultaneously? If this is the case you might consider using the Avalon arbitration settings in SOPC Builder to specify that the DMA have, for example, &#39;20&#39; accesses to the read memory while the other master has &#39;1&#39; -- this will ensure that once the DMA is granted access to that memory, it gets 20 continuous accesses. Of course, this may not be the problem, if the memory or peripheral you&#39;re reading from has some sort of intrinsic delay after the first several accesses.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    To Jesse:

    Can you explain to me that the mean of "while the other master has &#39;1&#39; "?

    Thank you!