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Altera_Forum
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15 years ago

DMA transfer inside ISR: Problem

Hi everybody, I think this is a common issue, but I didn't find a solution to my question, so hopefully I will get an answer here: I have a DMA controller which I want to use on an IRQ com...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi DSL!

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For (1) you need to ensure that the cache line is invalid at the start.

For (2) you need to ensure that the ends of the memory block aren't shared with anything else.

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For (1): why the cache line have to be INVALID (?!) at the start? What this means? And how I could test it?

For (2): how can I ensure that the memory block aren't shared with anything else? This work is not made by the compiler?

Regards