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Altera_Forum's avatar
Altera_Forum
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15 years ago

DMA transfer inside ISR: Problem

Hi everybody, I think this is a common issue, but I didn't find a solution to my question, so hopefully I will get an answer here: I have a DMA controller which I want to use on an IRQ com...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi! Thank you so much for your fast response!

Yes, in my system I have a processor NiosII/f with data and istruction cache (look the attachment). In my system I use an external SRAM and a little on_chip_memory (4096 Bytes) which is used also for exception vector. If I read the address of buffer it seems that it's always allocated in external SRAM in all previous cases.

How can I bypass the cache and read the values direct from the ram?!

Thanks for your help!

(http://www.answerbag.com/q_view/1182695#ixzz13xxzrkvj)