DMA to on-chip RAM

OK, I'm going to chalk this one up to a bug in SOPC builder...

After adding the internal SRAM, I started to generate the design. Then, realising I hadn't hooked up the DMA controller read/write masters and the CPU instruction master was also hooked up to the on-chip ram, I stopped the generate.

I made the changes and hit 'generate' again. Re-built in Quartus and I couldn't get this design to DMA to the on-chip RAM. I know I re-generated the design b/c it wouldn't have built a design I stopped half-way thru the generate - right?!?

Anyway, when that didn't work, I was looking thu the generated VHDL for some signals I wanted to snoop in Signal-Tap and noticed that the CPU instruction master was still hooked to the on-chip RAM! Huh!?! Went into SOPC builder again, and re-generated the design. This time - it looked like it should!

And now it works.

I can't see that it was merely a case of 'forgetting' to do something? The design definitely built the 1st time 'round, b/c it was the first and only design to have on-chip RAM, which was definitely working.

I can only put it down to SOPC builder not re-building *everything* after I hit 'stop' and then made changes to the bus interconnect and re-generated!

That&#39;s my story - and I&#39;m sticking to it! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

Regards,

Mark