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Altera_Forum
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21 years ago

DMA SPEED PROBLEM!

I have system with 3 SDRAM controllers 1'st is x16 SDRAM for storing code and data (MAIN_SDRAM) 2,3 is x8 for video memory (V1_SDARM,V2_SDRAM) All SDRAMs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hello,baycool!

I'd like to know your sram's setup time, hold time, wait clok setting in sopc builder.

If your sram is a lentency off-chip slave maybe this is dma speed neck and not sdram.

Now avalone-tristate bus don't support variable latency off-chip memory that works in

burst mode with latencys master.( avalon bus manual p-78)

You've tried?