DMA SPEED PROBLEM!

Hello,

I am using Nios II 1.1 and the DMA with Quartus 4.2 SP1.

In my system I have only the DMA as the READ_MASTER of SDRAM . The Nios executes out of SRAM.

I Have the the Tri bridge that the SRAM is on as the target of the WRITE_MASTER of the DMA.

I have using the HAL paradigm and have put the DMA in a streaming mode where it reads from the same module, SDRAM in this case.

I have played with the burst length changing that from 1024 bytes up to 4096 bytes, and got only about 30 Mbits/s in both cases. I then changed the arbitration for the SDRAM to 100 shares of 102, even though the processor fetches its instructions out of RAM. I have even increased the instruciton cache to see if this would make a difference.

I all cases I peak at around 32 Mbits/s.

I have tried to read most of the DMA threads about SDRAM performance and still don't see a straight forward way to see atleast a few 100Mbits/s performance out of the SDRAM.

I have read and been told that the system I have, while it does not formalize bursting like Nios5.0, it still should move data on every clock cycle, with overhead of course reducing this.

Even though this is an old topic can someone shed light on how to see decent SDRAM reads with a DMA?

Thanks