DMA SPEED PROBLEM!

Alex,

What I am suggesting with arbitration priorities will give you as good as performance as can be had with a burst, provided that the arbitration 'share' you enter into SOPC Builder is your burst size... if you assign 100 to the DMA and 1 to the CPU, and the DMA then attempts to transfer 100 (or more) words, it will get un-interrupted access to SDRAM for 100 accesses at a time. Since the accesses are sequential, after the initial few clocks to get the data moving you'll store or load one word of data per clock (of course there will be delays for switching banks and occasional refreshes as there would be in any SDRAM interface, but these are not too great).

That said our current DRAM controller does not have explicit burst support, but again, if the addresses presented to it are sequetial and the master is latency aware (which the DMA is), you'll get burst performance.

The disadvantage of the above is that you rob the CPU of SDRAM access, assuming that a single SDRAM chip is shared between Nios data/instructions/DMA budfer... in the code sample you gave this is no problem, but in a more complex multi-threaded system this may be an issue unless your other code which is running is cached.

Out of curiosity, what is your bandwidth requirement for this application for the DMA transfer, and what is your clock speed?