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Altera_Forum
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21 years ago

DMA SPEED PROBLEM!

I have system with 3 SDRAM controllers 1'st is x16 SDRAM for storing code and data (MAIN_SDRAM) 2,3 is x8 for video memory (V1_SDARM,V2_SDRAM) All SDRAMs...
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Altera_Forum
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21 years ago

One other idea, if you must share Nios II program/data memory with your DMA source: In SOPC Builder go to view --> "arbitration priorities". Now, look at the integer for the connection between DMA and SDRAM. Increase the number >> than the CPU. For example, if the CPU is set to 1, set the DMA master to 8 or 16 (or higher).

What this does is tell the SOPC Builder arbitration logic, during contention between CPU and DMA, to allow 8/16 transfers to/from the DMA for every single transfer from the CPU. This should grealy improve throughput during times of contention, as the SDRAM won't be "thrashing" around constantly going from one bank to another. Altera app note 184 (now somewhat dated) discusses this briefly; some more comprehensive documentation on this will be put up on the Altera web site soon.