Honored Contributor
Honored ContributorHI, i found your posto on Nios forum, i'm working on same target, a fifo used with DMA.
Can you tell me as you have solved the problem of busy flag ? second question.... i have configured the dma to work only from dram to fifo, in this case the write address of dmna register, is the sigle location definied into sopc builder ? (i have instantiated the fifo inside the sopc) regards Roberto roberto.buti@virgilio.it --------------------------------------------------- Please note that Nios Discussion Board has no control over the contents of this message. --------------------------------------------------- Regards, The Nios Discussion Board team. http://www.niosforum.com/forum/index.php (http://www.niosforum.com/forum/index.php) I had few some problems, because I was waiting to do the transfert on PIO edge and PIO was too long. But the problem on the DMA was the control register, if it hadn't a good value it can made your system do anything or the doing "printf" not writing to screen. I think that you should care a lot of attention to the control register. I had try to use the Hal fonction library but in thes case of stream mode, it works only if you change the control register with ioctl. Could you give me the part of code which control the DMA? for your second question, I don't know if the write register is at the base but i tkink yes.
