hi ! i would like to start implement DMA controller with uart I already generate and download my system into fpga startix II dev board succefully . I saw also documents about DMA , bit into status and control register . To increase performances in my application i would like to use DMA with uart . In this case i need transaction between Ram to uart and vicerversa, try to image a communication RS485 . My fpga will be a master of RS485 com. and then send data from ram to uart , and receive data from uart to ram . When interrupt end transaction occur i process buffer in I would like to know wich important steps i have to follow thanks walter

for example i have to send this structure data do uart typedef struct RS485{ float data1; float data2; int data3[10]; long data4; }mydata; with sizeof(mydata) i can know the lenght of datas to send but there is not addressof(...) function to know the address in memory of my data structure ; The function alt_dma_txchan receive differents arguments , i can put &mydata instead the address in memory , i will try but where i specifie the uart ? thanks walter ciao

i tryed different way . In sopc builder connecting write port dma to ext bus ram and read port dma to uart. After setting flag end of packet for the uart After without setting end of packet i wrote following code : # include "dma_test.h" typedef struct COMM { float data1; float data2; float data3; int data4; int data5; int data6; int data7; }Master; Master data_send; # define DMA_0_STATUS_REG 0# define DMA_0_READ_ADDR_REG 1# define DMA_0_WRITE_ADDR_REG 2# define DMA_0_LENGHT_REG 3 # define DMA_0_CONTROL_REG 6 int main(void) { data_send.data4=10; data_send.data5=100; data_send.data6=33; data_send.data7=44; IOWR(DMA_0_BASE,DMA_0_READ_ADDR_REG,&data_send); IOWR(DMA_0_BASE,DMA_0_WRITE_ADDR_REG,UART_0_BASE); IOWR(DMA_0_BASE,DMA_0_LENGHT_REG ,28); IOWR(DMA_0_BASE,DMA_0_CONTROL_REG ,ALTERA_AVALON_DMA_CONTROL_BYTE_MSK | ALTERA_AVALON_DMA_CONTROL_GO_MSK | ALTERA_AVALON_DMA_CONTROL_WCON_MSK ); printf("data_send:%u\r ",sizeof(data_send)); while(true) { } return(0); } i set fixed address for write port dma (uart) and else but nothing was sent . i can&#39;t understand what i need and what i have to do Impossible to find good documentation for dma-uart , what to do in sopc builder and what to do in sw. Maybe need to set something for the uart ,but how I need this to communicate different devices fpga in a new project but if i don&#39;t know dma-uart i will make sending one byte at time , and load cpu for increasing buffer receive and transmiter . Uncredible ..... not possible to find more informations about this ciao walter

better forget dma and nios II also http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif

Page 4-19: http://www.altera.com/literature/hb/nios2/n2sw_nii52004.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii52004.pdf)

pmicro, It should be possible to use a DMA to setup a streaming transfer from/to a block of memory... From what you&#39;ve mentioned, I believe you have a custom UART, so you should be aware that you do have to make sure that your UART supports streaming transactions. BadOmen already pointed you to the resource on the DMA and there is a similar resource for the Avalon UART. Please explain both your hardware and your software a bit better...and try to get simple memory-to-memory transfers working...first, with the DMA. ...and get an attitude improvement injection :-) This is, after all, a free forum! Cheers, - slacker

DMA and Uart | Altera Community

13 Replies

Altera_Forum
Honored Contributor
19 years ago
what i have to do ?
create a system multiprocessor , where one cpu works for the
communication .
Otherwise the dma is a avalon master like a cpu .
If i use one cpu for logical processing and an other cpu for the communication
i should resolve my problems .
Anyway if i choose this system , may i share variables for two cpu?
for example with the cpu n°1 i get and send data and
put them in memory with name (struct mydata), and with cpu n°2 that i use for logical processing may i read and write the same variable (struct mydata) ?
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif
Altera_Forum
Honored Contributor
19 years ago
ok i found an old post about dma -> uart
i copy and paste and now run successfull , better then nothing
ciao
walter
Altera_Forum
Honored Contributor
19 years ago
--- Quote Start ---
originally posted by pmicro@Jun 22 2006, 12:50 AM
anyway if i choose this system , may i share variables for two cpu?
for example with the cpu n°1 i get and send data and
put them in memory with name (struct mydata), and with cpu n°2 that i use for logical processing may i read and write the same variable (struct mydata) ?
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=16325)
--- quote end ---

--- Quote End ---

Yes, in general you can share data among different CPUs. There are different ways to do that. I typically use the one we developed for ERIKA Enterprise, it is quite simple because it allows you to share data structures without changing the source code using them...

bye

Paolo

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DMA and Uart

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