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NIJGNAS's avatar
NIJGNAS
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1 month ago

DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails

Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 ...
Nios Architecture
Nios Cpu
NIJGNAS's avatar
NIJGNAS
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1 month ago

Hi SteveK_Arrow,

I tested that. After the JTAG chain problem occurred, I power-cycled the board and tried scanning again.

Result: no change. JTAG Auto Detect still fails after the power cycle on both:

  • embedded JTAG, and
  • external USB-Blaster II via J10.

 

The JTAG Chain Debugger continues to show the same behavior (unknown devices, chain problem) as before. 'jtagconfig --debug' shows the same.

Thanks.

SteveK_Arrow's avatar
SteveK_Arrow
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1 month ago

Hi NIJGNAS

Is the QSPI device flashed with content? What are the MSEL DIP switch SW2[1:4] settings? Are they set to configure using JTAG or Avalon streaming interface x8?

Thanks

  • NIJGNAS's avatar
    NIJGNAS
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    1 month ago

    Hi,

    Yes, the QSPI is flashed with content. 

    • With SW8.2 = ON (FPGA removed from the JTAG chain), I was able to Program and Verify the factory recovery image AVSTX8.pof into the QSPI successfully. In this mode, the JTAG chain shows only the MAX10 (10M50DAF256) and the QSPI_2Gb device (see attached JTAG chain screenshot).
    • If I try to program without removing the FPGA from the chain (SW8.2 = OFF), the programming fails with:

    Error(209062): Flash Loader IP not loaded on device 2

    Error(209012): Operation failed

    • After successfully programming the QSPI (with SW8.2 = ON), switching SW8.2 back to OFF still does not restore JTAG. Quartus Programmer Auto Detect continues to fail (same behavior on both embedded JTAG and external USB-Blaster II).

     

    Regarding MSEL DIP SW2[1:4]:

    • Only when I initially ran the Nios V Hello flow, SW2[1:4] was [OFF:OFF:OFF:OFF] (JTAG).
    • Since then, SW2[1:4] has been kept at [ON:OFF:OFF:OFF] (AVST x8) and has not been changed.

     

    Thanks.

    • SteveK_Arrow's avatar
      SteveK_Arrow
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      1 month ago

      Hi

      I am interested in knowing what happens to the JTAG chain if we disable the FPGA from configuring from the QSPI.

      Could you set SW2 so that it is in JTAG mode [OFF, OFF, OFF, Reserved] and SW8.2 = OFF so that the FPGA is reinserted into the JTAG chain? Then rescan.

       

      Thanks

      • NIJGNAS's avatar
        NIJGNAS
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        1 month ago

        Hi,

        I just tried the exact setup you suggested to disable configuration from QSPI and reinsert the FPGA into the JTAG chain:

        • SW2[1:4] set to JTAG mode: [OFF, OFF, OFF, OFF]
        • SW8.2 = OFF (FPGA reinserted into the JTAG chain)
        • Then I rescanned the JTAG chain (Quartus Programmer Auto Detect / JTAG Chain Debugger)

         

        Result: no change compared to before. Auto Detect still fails, and the JTAG Chain Debugger shows the same JTAG chain problem and the same error messages as previously reported.

        Thanks.