Altera_Forum
Honored Contributor
Honored ContributorDigital Pll
hi any one can explain concept of digital pll and how to implement it in cyclone3
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Altera_ForumHonored Contributor
Honored Contributorhi..thank u for your reply..
my requirement is , i want to lock 32MHz clock from vcxo which is going to fpga with reference clock of 2MHz which is also coming to fpga.(ie both should be in sync)
