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Altera_Forum
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15 years ago

Design with a Stratix device with no external memory

I have a problem that I need help to solve. I have been given the task to complete a Stratix FPGA design. The PCB board is already complete and no external memory for the FPGA was included in the des...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Larry, which Stratix device you are using? You need more onchip memory if you haven't external one. You can change this in SOPC builder. If you don't have enough ram resources you have to reduce your code. Running Iniche Stack in superloop mode instead of using uCosII is a possibility. Other way is to use a smaller TCP/IP stack. For older Nios2 versions Altera was providing a so called lightweigt IP stack. But it I think it wokrs only for 10/100 Ethernet (with LAN91c111 MAC Chip).

An other way to reduce code is discussed here:

http://www.alteraforum.com/forum/showthread.php?t=18376&highlight=lightweight (http://www.alteraforum.com/forum/showthread.php?t=18376&highlight=lightweight)

I'm using Iniche in superloop mode and TSE-Mac from Altera. Depending on firmware I need about 275 up to 340 kBytes (external) RAM.

What do you mean with slave mode operation? May be you could transfer a reduced TCP/IP protocoll engine to hardware. But you have to change/extend the FPGA design in that case.

Jens