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Altera_Forum
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15 years ago

Design with a Stratix device with no external memory

I have a problem that I need help to solve. I have been given the task to complete a Stratix FPGA design. The PCB board is already complete and no external memory for the FPGA was included in the design. My problem is I receive the errors below from Nios II when I compile. The modules are ones that are part of Simple Socket server and are shown below:

Severity and Description

ld: region main_memory is full (Stratix_050110.elf section .text). Region needs to be 165780 bytes larger.

ld: section .bss [030088b4 -> 030102af] overlaps section .text [030001f0 -> 03041793]

ld: section .rodata [03000040 -> 03006693] overlaps section .exceptions [03000040 -> 030001ef]

ld: section .rwdata [03006694 -> 030088b3] overlaps section .text [030001f0 -> 03041793]

Modules below that are included with the Simple Socket Server.

alt_error_handler.h

network_utilities.h

simple_socket_server.h

alt_error_handler.c

iniche_init.c

network_utilities.c

simple_socket_server.c

Are there modules that get included that I can eliminate to reduce the required memory? How can I find out how to strip down memory usage. My design includes 96 FIFO which are 1024 samples X 12 bits of data X 96 channels. I am also using 1000B Ethernet, but only need a slave mode operation. I am not a FPGA designer. Is there anybody that can help me?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Larry, which Stratix device you are using? You need more onchip memory if you haven't external one. You can change this in SOPC builder. If you don't have enough ram resources you have to reduce your code. Running Iniche Stack in superloop mode instead of using uCosII is a possibility. Other way is to use a smaller TCP/IP stack. For older Nios2 versions Altera was providing a so called lightweigt IP stack. But it I think it wokrs only for 10/100 Ethernet (with LAN91c111 MAC Chip).

    An other way to reduce code is discussed here:

    http://www.alteraforum.com/forum/showthread.php?t=18376&highlight=lightweight (http://www.alteraforum.com/forum/showthread.php?t=18376&highlight=lightweight)

    I'm using Iniche in superloop mode and TSE-Mac from Altera. Depending on firmware I need about 275 up to 340 kBytes (external) RAM.

    What do you mean with slave mode operation? May be you could transfer a reduced TCP/IP protocoll engine to hardware. But you have to change/extend the FPGA design in that case.

    Jens