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Altera_Forum's avatar
Altera_Forum
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15 years ago

desig testbench

We are VLSI design center and we made several designs before, using FPGAs, by writing the required codes and testbench for functional and timing simulation of the design, then download the design on the hardware . Currently we have a design that uses IPs only . We implemented it using SOPC builder and we have also a development board for hardware testing .

My question is : do we need to write the testbench for this design in order to perform functional simulation first then download it on the development board ? or can we skip the functional simulation since the design consists of IPs only and these IPs are tested by Altera?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    We are VLSI design center and we made several designs before, using FPGAs, by writing the required codes and testbench for functional and timing simulation of the design, then download the design on the hardware . Currently we have a design that uses IPs only . We implemented it using SOPC builder and we have also a development board for hardware testing .

    My question is : do we need to write the testbench for this design in order to perform functional simulation first then download it on the development board ? or can we skip the functional simulation since the design consists of IPs only and these IPs are tested by Altera?

    --- Quote End ---

    Hi,

    in my experience it is always good to have a functional simulation in place, in order to have a reference in case something does not work as expected in hardware. Maybe you assigned a signal to a wrong pin etc.....

    Kind regards

    GPK