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Honored Contributor
Honored ContributorDebugging NIOS2 + Verilog code
We are using a Stratix processor with NIOS2 (Altera University Program DE4 development board with a Stratix Ep4SGX230KF40C1 processor). We have been plagued with problems where small changes in code ...
Altera_ForumHonored Contributor
Honored ContributorHow many unconstrained paths? Because if you end up with entire unconstrained clock domains, it's possible that a big part of your design isn't analysed by Timequest at all, and you could have timing problems. Timing problems are one of the most common causes of erratic behaviours.
At least try to constrain all your I/O and clocks, and check in Timequest's clocks report that they are all there, with the correct frequencies.
