Debugging Issue with Nios® V Processor Using Ashling RiscFree IDE on Agilex® 7 FPGA

Hello,

We are encountering an issue while debugging our application on the Nios® V processor implemented on an Agilex® 7 FPGA, using the Ashling RiscFree IDE. The problem occurs after the first successful debug session. When attempting to debug the application a second time, the debugger jumps to the following section of code in crt0.S:

#if ALT_CPU_HAS_CSR_SUPPORT
/* assume that we are in machine mode on startup */
/* setup trap to catch anything that goes wrong early in the boot process */
la t0, trap_vector
csrw mtvec, t0

/* disable all interrupt */
li t0, 0x88
csrc mstatus, t0
csrw mie, zero
csrw mip, zero
#endif

At this point, we receive the error:
Error: Operation failed: "Command Aborted"

To debug the application again, we are forced to reprogram the FPGA with the SOF file each time. We are looking for a solution to avoid this reprogramming step while debugging repeatedly.

Additional Observations

• Run Mode Works: Using "Run As > 3 Ashling RISC-V Hardware Debugging" allows us to run the application multiple times without reprogramming the FPGA.
• Connection of dbg_reset_out: Following the guidelines in "AN 978: Nios® V Processor Migration Guidelines," the dbg_reset_out signal is not connected to the reset signal of the Nios® V. However, we tested connecting these signals, but it made no difference to the issue.
• QSYS Configuration: We have attached an image showing the connections of the various subsystems in the Platform Designer (QSYS).

Could you please advise us on how to address this issue?

Thank you in advance for your assistance!