Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Debugging CPU failure

Hello all, I run a Nios II/f processor on a Stratix II S30 device, the software working in unison with a VHDL design on the same chip. The system runs in a high-noise environment, and I have sp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Thanks for the tips - my design is fully synchronous, and in fact my VHDL inside that FPGA keeps working even after the Nios software is knocked out. I'm still interested to know how I can analyze the failure of the Nios software (without using a debugger, which doesn't work in my environment because of the noises affecting the USB blaster).