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Altera_Forum's avatar
Altera_Forum
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20 years ago

Debug problem, need help!

I had buid a small system in SOPC Builder 5.0 with NIOS II/F, JTAG level 3, 8KBytes onchip_rom, 4KBytes onchip_ram, jtag_uart, and a output only PIO module. In NIOS IDE, I compiled a sample pr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

The Byteblaster II cable is not supported for debug. That being said, it should still work, but you've got to make sure your JTAG chain is very clean.... Try running SignalTap II on your Quartus II design. If it fails with some sort of JTAG communications error, you've got signal integrity issues.

In any case, you ought to get a better solution for d/l and debug. I'd recommend a USB Blaster, or, if you can't afford one, try the EZNIOSUSB from EasyFPGA.

Cheers,

- slacker