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Did you upload the provided .sof file to the FPGA before uploading the software or did you upload a .sof file you compiled yourself from the full featured project?
In the latter case, if you don't have the license for the Nios CPU and some other componenst (such as Ethernet) then your design becomes time limited (it goes into a *_time_limited.sof file) and if you close the evaluation window then all the licensed IP (including the Nios processor) will stop working.
If this isn't the case, the reasons for a Nios CPU not to respond are usually basic, i.e. a bad clock or reset signal. Is there a reset switch on the board that could be stuck?
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The supplied .SOF that was in the example directory inside of the instalation folder of the niosII ide.
IM still pretty green to this enviroment so I just wanted to see something run before I started writing code.
as far as clock, since I did not compile the HDL on quartus (i'm just flasing the .sof) that has't been changed, only if there is a physical switch that Im unaware about.
I did actually try to open the quartus II project file in quartus and cheked on pin assignment that the n_reset line is assigned to pin_c5 which it isn't very clear, but in some research, that pin supposedly is connected to the Audio codec.
Now it seems very weird to me because, I think Altera, or terasic wouldn't make such a mistake in providing that .sof file with such an error, or if they would someone here would have ran into it.
as it is a very common development boad. the DE2 is .
So Im actually stuck, Now, in the same board I was able to run a different .sof file , provided with the Textbook Im following the it ran fine without a hitch. so... I dont know now..
we actually have two board, and both problems show on both ( we are trying to finish our final project on this board, and it requires two distinct boards)
By the way, I do know about the time limited thing , I had ran into it before, during a tutorial so I know what to do when I see that.
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