DE2 JTAG_UART terminal_PC communication problem : pausing target proccessor

Hi,

I have rebuild all and the result dont change.

0-Copy in new work file the nios2eds example project: C:/altera/91/nios2eds/example/verilog/nios2_cyclone II_2c35/standard/*

1-Open QII (9.1 sp1 web edition ips-embedded license)-> open NiosII_cycloneII_2c35_standard project -> SOPC Builder ->automate base-address ->generate project :

-warning : using ddr_sdram_0 module version 9.11 and not 9.1

- i can read at sysid module/ the id system and timestamp

- sopcinfo file generated

2-Compile QII project

- *.sof generated

-DE2 cyclone II 2c35 FPGA configure : download *.sof

3-Open nios2 EDS BTS

- Workspace : same that QII project

- New File : nios2 application and BSP template

- Location SOPC : same that QII project

- hardware : nios2_cycloneII_2c35_sopc.sopcinfo

- Project name: hello_world

- ../software/hello_world and ../software/hello_world_bsp created

-build hello_world_bsp project

-build hello_world project

- i can real in public.mk file the id system and timestamp paremeters

- i dont understand WHAT IS syslib (¿old IDE file version?)

- hello_world RUN AS nios hardware

4-Error: sys id not found at base address

¿ there is some other file from original example that is not upgrade when i build sopc, compile qII project and create hello_world software and bsp? Then makefile and socpinfo are ID matched, why can not execute the download-nios2 *.elf command?

I have tried look for other example with sysid peripheral but i dont get it

Thanks