DE0 with uClinux

This is probably something wrong with the SDRAM interface. Either bad pin assignments or bad timing.

If you FPGA is big enough you could design a system with some on-chip RAM and then run a memory test application from there to test the SDRAM. For that you will need to create a new BSP that uses the on-chip RAM for all sections (text, bss, data), compile with "optimize for space" and the small C library, and select the memory test template when you create your application.