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Altera_Forum
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11 years ago

DDR3 on Cyclone V E

Hi I would like to connect the MT41J128M16JT-125 with the uniPHY to my Cyclone V E as a hard memory interface. My clk_0 is 50MHz and the Systemclock is 80MHz. I connected the cmd and fifo...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The phase shift of PLL is tVCO/8.

In that case, it seems like your fVCO is 300Mhz.

Thus each phase shift step is 417ps.

So you wont be able to set to 500ps.