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Altera_Forum's avatar
Altera_Forum
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20 years ago

DDR2 interface

Hi

I'm using in my aplication the DDR2 module by Samsung (M378T3354CZ3).

after implementing and generating in the SOPC I have received many I/O interfacing the module that I do not know how to connect (e.g. startix_DLL_control or dqsupdate_to_DDR2 etc.)

I would like to get a ref. design using this DDR2 sdram controller so I can understand how to connect, or is there any updated documents explaining the different interfaces?

Thanks

Ariel

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hello,

    The Nios II Development Kit, Cyclone II Edition is working with DDR memory. You can use this one as a reference design. The documentation comes with the Nios II installation.

    Regards,

    niosIIuser
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi

    Thanks for the information but on the cyclone II it is for DDR and not DDR2.

    there are some differences between the two and this is why I need ref. design.

    Regards,

    Ariel
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    You can look at CycloneII DSP dev board from Altera. It has the DDR2 modules.

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by hippo@Feb 27 2006, 09:57 PM

    you can look at cycloneii dsp dev board from altera. it has the ddr2 modules.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12976)

    --- quote end ---

    --- Quote End ---

    Hi hippo

    can you send me the DSP full featured design so I can look at it

    I do not have the design

    Thanks

    Ariel
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi Hippo

    on the site there are no Quartus reference designs only information regarding the board design.

    regards

    Ariel
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by hippo@Mar 1 2006, 08:09 AM

    i made some study on it. it seems to be in the cycloneii dsp kit&#39;s setup program. and not available on the web. http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/sad.gif

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13026)

    --- quote end ---

    --- Quote End ---

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    When you generate the DDR2 core click on the advanced checkbox. Go to project settings and make sure that the checkboxes for update example design and example pll are checked. Then just look at the top level example design file generated by the IP megacore. It shows all of those signals and how to connect them. And no your core will not work at all if you don&#39;t get it exactly right.