Hi friends, I want to control DDR2 and Ethernet with NIOS II on my board. ADC results are read from LVDS_rx module and store on DDR2 and then stream out via Ethernet. On my board, there is no SDRAM except for a DDR2, so I want to use on-chip memory for Nios ii . Can I get it? Any advice and guidance will be appreciated.

I use cyclone III ep3c25f324. Is there enough on-chip memory for my project ? Need your help , thanks.

Why not using DDR2 memory? It doesn't matter what memory type it is, since You need to use either DMA (better SGDMA for faster transfers) or write Your own Avalon Memory Master controller. How fast ADC is?

You can put your code+data into internal memory (probably tightly coupled) while still using the external DDR2 memory for large items (like the ethernel buffers). However you may have to be careful about the size of the code. I don't know how small the TCP/IP stack can be, but even the 'hello world' program pulls in enough stuff from libc to be a little large for internal memory. My suspicion is that the IP stack won't be that concise! Enough code to send IPv4 UDP packets should be quite small, but you'll need something to give the system it's IP address. OTOH if you avoid all of libc, you can do quite useful stuff using internal memory.

--- Quote Start --- Why not using DDR2 memory? It doesn't matter what memory type it is, since You need to use either DMA (better SGDMA for faster transfers) or write Your own Avalon Memory Master controller. How fast ADC is? --- Quote End --- 400Msps ADC. DDR2 memory is used to store ADC result . if it's used for nios II ,what about the ADC ?

Attached is a snap of cyciii spec. , I use ep3c25 and how many on-chip memory can I use for nios ii cpu?

DDR2 and Ethernet | Altera Community

13 Replies

Altera_Forum
Honored Contributor
14 years ago
Sure, why not. If You'll use SGDMA, then You can allocate memory using malloc() or use fixed value.
Altera_Forum
Honored Contributor
14 years ago
OK，I'll try it. Thank you!
Altera_Forum
Honored Contributor
14 years ago
I'm not sure what the minimum M9K footprint for a nios cpu is, but it is relatively small!
- 1 M9K for the registers
- Remove the dynamic branch prediction logic (this is a 'hidden' option)
- Read code from tightly coupled memory
- No data cache, data can be in the same M9K as the code
- No JTAG debug
- Boot directly from the instruction memory (no separate M9K for epcs (etc) boot)
- Write small, tight code without any libc bloat and with minimal wrapper layers.

Forum Discussion

DDR2 and Ethernet

13 Replies

Recent Discussions

Ashling RISC Free IDE fails to download ELF file

Dual Port Nios V BSP error

set_output_delay explained for dummies

[Test only]How to verify Agilex 3 in radiation tolerant environment

gdb server problem when debugging