Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DDR2 and Ethernet

Hi friends, I want to control DDR2 and Ethernet with NIOS II on my board. ADC results are read from LVDS_rx module and store on DDR2 and then stream out via Ethernet. On my board, there is no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I'm not sure what the minimum M9K footprint for a nios cpu is, but it is relatively small!

- 1 M9K for the registers

- Remove the dynamic branch prediction logic (this is a 'hidden' option)

- Read code from tightly coupled memory

- No data cache, data can be in the same M9K as the code

- No JTAG debug

- Boot directly from the instruction memory (no separate M9K for epcs (etc) boot)

- Write small, tight code without any libc bloat and with minimal wrapper layers.