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Honored Contributor
Honored ContributorDDR vs. SDR RAM...
Anyone know if DDR Ram will fare better with the NiosII data master than SDRAM? After Dirk figured out it takes a whopping 12 clocks @50MHz (~240ns) per SDRAM read when not using the dma, we re...
Altera_ForumHonored Contributor
Honored ContributorHi Thomas,
In your analysis you have the Nios+SDRAM controller consuming 11-3 = 8 clocks. That's 8 clocks of overhead. Is this just to be expected as normal? How much overhead would be added on say a Coldfire or an ARM or some other softcore? Do all/most embedded processors add over 300% overhead to memory reads? I don't know for sure, but it doesn't sound right. I'd like to establish this as either an oversight, a work in progress, or the way it is and then have it documented. The current literature promises either "single cycle" or ">1 clocks" to access sdram. (11 != 1) Thanks, Ken
